rtl · GitHub Topics

#安卓#MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use L...

autolayout Android iOS uitableview uicollectionview constraints rtl grid-layout layout view CSS ui cocoapods Xcode

Objective-C 4.42 k

1 年前

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala 4.3 k

2 天前

chipsalliance / rocket-chip

Rocket Chip Generator

Scala rocket-chip chip-generator chisel RISC-V rtl

Scala 3.47 k

19 天前

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++ 2.95 k

3 天前

layoutBox / PinLayout

#IOS#Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

Swift layout-engine carthage cocoapod swift-library iOS layout rtl anchor ios-ui swift-framework language

Swift 2.4 k

1 年前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 2 k

1 天前

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V boom chisel rtl rocket-chip Scala

Scala 1.92 k

1 个月前

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rocket-chip chip-generator chisel RISC-V rtl soc peripherals chipyard boom Rocket

Scala 1.87 k

2 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala 1.8 k

2 天前

MohammadYounes / rtlcss

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

ltr rtl CSS 国际化 (i18n)mirror flip right-to-left PostCSS

JavaScript 1.7 k

4 个月前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.51 k

4 个月前