Verilator open-source SystemVerilog simulator and lint system
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
5-stage pipelined 32-bit MIPS microprocessor in Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
A place to keep my synthesizable verilog examples.
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
A playground based on the classic version of the Cloud V IDE
Digital System Design Verilog Implementation
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University
A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops
This Repository shows the implementation and results of various codes that I write in Verilog HDL
32-bit MIPS processor fully supporting all core instructions
The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital sys...