🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
RISC-V microcontroller IP core developed in Verilog
A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the perip...
The Antikernel operating system project
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
A Modeling and Verification Platform for SoCs using ILAs
Development platform for the Espressif ESP32 WiFi/Microcontroller SoC
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Small Processing Unit 32: A compact RV32I CPU written in Verilog
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
An open-source 32-bit RISC-V soft-core processor