yosys · GitHub Topics

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.51 k

4 个月前

cariboulabs / cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

sdr 软件 defined radio Robot Framework raspberry pi rpi fpga ice40 yosys

C 1.22 k

4 个月前

nturley / netlistsvg

draws an SVG schematic from a JSON netlist

yosys diagram 可视化 elk

JavaScript 704

1 年前

olofk / edalize

An abstraction library for interfacing EDA tools

eda fpga xilinx yosys synthesis Simulation Verilog vhdl systemverilog verilator

Python 695

2 小时前

m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga Verilog yosys nmigen

Python 672

3 年前

zachjs / sv2v

SystemVerilog to Verilog conversion

systemverilog Verilog conversion yosys

Haskell 637

1 个月前

efabless / caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys openroad openram

Verilog 331

4 个月前

apfaudio / eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

electronics eurorack fpga hardware modular-synthesizers kicad synthesizer Verilog yosys

SystemVerilog 211

17 天前

PyFPGA / pyfpga

A Python package to use FPGA development tools programmatically.

fpga Python tcl yosys trellis

Python 137

3 个月前

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic openram openroad yosys

Verilog 135

3 年前

lushaylabs / tangnano9k-series-examples

Examples for the Lushay Labs tang nano 9k series

fpga yosys

GLSL 112

1 年前

chipsalliance / fpga-tool-perf

FPGA tool performance profiling

vpr fpga perf yosys conda-environment toolchain performance-analysis

Python 102

1 年前

forflo / yodl

A VHDL frontend for Yosys

vhdl yosys

C++ 102

8 年前

akilm / Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

chip Open Source yosys raven RISC-V

102

5 年前

ECP5-PCIe / ECP5-PCIe

Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe

pcie fpga yosys trellis

Python 97

2 年前

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

RISC-V Verilog formal-verification yosys hardware hardware-acceleration Cryptography Open Source mit-license crypto cpu research-project

Verilog 93

2 年前

dadamachines / doppler

Arduino compatible – Cortex M4F & FPGA Development Board

samd51 ice40 fpga Arduino yosys

6 年前

chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

yosys eda fpga xilinx xilinx-fpga toolchain

Verilog 83

1 年前

stnolting / neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga xilinx intel yosys soc RISC-V vhdl Verilog

VHDL 79

7 天前

mattvenn / fpga-sdft

sliding DFT for FPGA, targetting Lattice ICE40 1k

fpga Verilog fft yosys fourier

Verilog 77

5 年前