openroad · GitHub Topics

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda openroad openram asic asic-library skywater pdk magic

Python 3.18 k

8 个月前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 2 k

11 小时前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.51 k

4 个月前

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

eda rtl tcl def gdsii Verilog openroad timing-analysis lef opendb-database

Verilog 443

21 小时前

google / gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

asic eda openroad pdk

Makefile 399

2 年前

efabless / caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys openroad openram

Verilog 331

4 个月前

efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

asic eda gdsii lvs openroad pdk silicon Verilog vlsi flow

Python 294

4 个月前

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic openram openroad yosys

Verilog 135

3 年前

google / open-source-pdks

Index of the fully open source process design kits (PDKs) maintained by Google.

asic eda openroad pdk silicon skywater

3 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_pr

Primitives for GF180MCU provided by GlobalFoundries.

asic eda openroad pdk

Python 50

2 年前

daquintero / piel

Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.

openroad electronics optimization system Quantum Computing

Python 48

1 个月前

google / skywater-pdk-libs-sky130_fd_pr_reram

SKY130 ReRAM and examples (SkyWater Provided)

asic eda openroad pdk silicon skywater

3 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

7 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda openroad pdk

Verilog 26

3 年前

google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram

SRAM macros created for the GF180MCU provided by GlobalFoundries.

asic eda ip openroad pdk

Verilog 17

2 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0

9 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda openroad pdk

Verilog 17

3 年前

meeeeet / RTL-to-GDS-Implementation-of-SerDes

openroad Verilog

Verilog 17

1 年前

google / skywater-pdk-libs-sky130_fd_sc_hd

"High density" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 16

2 年前

The-OpenROAD-Project / ORAssistant

#大语言模型#OpenROAD's Chatbot Assistant

eda 大语言模型 openroad Python

Python 15

14 天前

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provide...

asic Linux openroad Open Source hardware

4 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_io

IO and periphery cells for the GF180MCU provided by GlobalFoundries.

asic eda io openroad pdk

Verilog 13

3 年前