asic · GitHub Topics

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

eda openroad openram asic asic-library skywater pdk magic

Python 3.18 k

8 个月前

openhwgroup / cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu asic fpga rv64gc ariane RISC-V

Assembly 2.51 k

4 小时前

olofk / serv

SERV - The SErial RISC-V CPU

Verilog fpga asic RISC-V

Verilog 1.6 k

11 天前

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.51 k

4 个月前

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell fpga vhdl Verilog systemverilog asic

Haskell 1.5 k

1 天前

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

RISC-V cpu Verilog fpga verilator rv32im rv32i asic verification

Verilog 1.48 k

4 年前

pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

systemverilog hardware asic fpga rtl ip

SystemVerilog 1.3 k

4 天前

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

RISC-V rv32i rv32im cpu fpga Verilog verilator asic branch-prediction Linux xilinx artix-7

Verilog 1.04 k

4 年前

siliconcompiler / siliconcompiler

Modular hardware build system

asic eda fpga hls make rtl synthesis Verilog vhdl

Python 1.03 k

12 小时前

ucb-bar / gemmini

Berkeley's Spatial Array Generator

asic dnn accelerator

Scala 964

2 个月前

riscvarchive / riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

RISC-V asic fpga

885

4 年前

esig / dss

Digital Signature Service : creation, extension and validation of advanced electronic signatures

asic signature esignature validation Java

Java 881

4 天前

ultraembedded / cores

Various HDL (Verilog) IP Cores

Verilog rtl fpga verilator asic audio i2s spi uart usb

Verilog 810

4 年前

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

vhdl verification systemverilog-hdl Unit testing fpga asic

VHDL 778

1 个月前

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

vhdl poc-library Python Simulation synthesis verification vlsi fpga hardware-designs asic xilinx regression-testing

VHDL 580

5 年前