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集合主题趋势排行榜

#

Verilog

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Website
Wikipedia: 维基百科

logisim-evolution/logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

logisim-evolution 教学 circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl Verilog

Java 5.84 k

6 天前

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga xilinx Verilog pynq

4.73 k

3 年前

chipsalliance/chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

chisel chisel3 Scala firrtl rtl chip-generator Verilog

Scala 4.3 k

1 天前

open-sdr/openwifi

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

fpga ofdm 802-11 zynq Linux xilinx analog-devices mac80211 csma dma Verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware

C 4.2 k

4 天前

verilator/verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

Verilog system-verilog verilog-simulator verilator compilers C++systemc rtl

C++ 2.95 k

3 天前

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl Verilog fpga

Assembly 2.8 k

7 天前

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V cpu core china Verilog nuclei

Verilog 2.73 k

4 年前

darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V Verilog fpga core

Verilog 2.34 k

23 天前

jbush001 / NyuziProcessor

GPGPU microprocessor architecture

fpga gpu-computing gpu Verilog hardware microprocessor graphics processor-architecture

C 2.09 k

7 个月前

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

Python vhdl Verilog verification Testing

Python 2 k

2 天前

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 2 k

1 天前

langhuihui / monibuca

🧩 Monibuca is a Modularized, Extensible framework for building Streaming Server

livestream mediaserver hls WebRTC rtmp rtsp Verilog WebSocket flv rtp ts

Go 2 k

4 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala 1.8 k

2 天前

pConst / basic_verilog

Must-have verilog systemverilog modules

fpga delay debounce encoder xilinx Verilog tcl synchronizer pwm uart hls

Verilog 1.8 k

2 个月前

stnolting/neorv32

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V vhdl fpga soc Microcontroller processor cpu system-on-chip embedded rtos smp multi-core Verilog

VHDL 1.79 k

2 天前

FPGAwars/icestudio

FPGAwars / icestudio

#编辑器#❄️ Visual editor for open FPGA boards

editor fpga blocks Verilog ide JavaScript

JavaScript 1.78 k

5 天前

amaranth-lang / amaranth

A modern hardware definition language and toolchain based on Python

Python 1.71 k

1 个月前

analogdevicesinc / hdl

HDL libraries and projects

analog-devices Verilog fpga Hacktoberfest

Verilog 1.67 k

2 天前

olofk/serv

SERV - The SErial RISC-V CPU

Verilog fpga asic RISC-V

Verilog 1.6 k

11 天前

riscv-mcu / e203_hbirdv2

The Ultra-Low Power RISC-V Core

RISC-V fpga hummingbird nuclei soc china Verilog cpu core

Verilog 1.52 k

8 个月前

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