fpga · GitHub Topics

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

john C ripper password jtr opencl gpgpu Assembly cracker crypt hash simd openmp gpu fpga mpi

C 11.7 k

1 个月前

PaddlePaddle / Paddle-Lite

#计算机科学#PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

移动深度学习神经网络 arm mdl baidu embedded mali fpga mobile-deep-learning

C++ 7.13 k

2 个月前

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

logisim-evolution 教学 circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl Verilog

Java 5.98 k

2 天前

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga xilinx Verilog pynq

4.85 k

3 年前

open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

fpga ofdm 802-11 zynq Linux xilinx analog-devices mac80211 csma dma Verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware

C 4.27 k

13 天前

enjoy-digital / litex

Build your hardware, easily!

fpga hardware system-on-chip

C 3.43 k

2 天前

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl Verilog fpga

Assembly 2.83 k

1 个月前

openhwgroup / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

systemverilog-hdl cpu asic fpga rv64gc ariane RISC-V

Assembly 2.57 k

3 天前