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fpga

https://static.github-zh.com/github_avatars/openwall?size=40

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

C 11.95 k
13 天前
https://static.github-zh.com/github_avatars/PaddlePaddle?size=40

#计算机科学#PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎)

C++ 7.15 k
4 个月前
https://static.github-zh.com/github_avatars/LeiWang1999?size=40

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

4.96 k
3 年前
https://static.github-zh.com/github_avatars/enjoy-digital?size=40
C 3.5 k
2 天前
https://static.github-zh.com/github_avatars/SpinalHDL?size=40

A FPGA friendly 32 bit RISC-V CPU implementation

Assembly 2.88 k
2 个月前
https://static.github-zh.com/github_avatars/openhwgroup?size=40

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Assembly 2.62 k
6 天前
https://static.github-zh.com/github_avatars/darklife?size=40

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2.41 k
2 个月前
https://static.github-zh.com/github_avatars/GlasgowEmbedded?size=40
Python 2.04 k
18 小时前
https://static.github-zh.com/github_avatars/corundum?size=40

Open source FPGA-based NIC and platform for in-network compute

Verilog 2.01 k
1 年前
stnolting/neorv32
https://static.github-zh.com/github_avatars/stnolting?size=40

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1.86 k
12 小时前
https://static.github-zh.com/github_avatars/SpinalHDL?size=40
Scala 1.85 k
1 天前
https://static.github-zh.com/github_avatars/pConst?size=40
Verilog 1.84 k
2 个月前
FPGAwars/icestudio
https://static.github-zh.com/github_avatars/FPGAwars?size=40
JavaScript 1.82 k
1 个月前
https://static.github-zh.com/github_avatars/amaranth-lang?size=40

A modern hardware definition language and toolchain based on Python

Python 1.78 k
14 天前
https://static.github-zh.com/github_avatars/analogdevicesinc?size=40
Verilog 1.74 k
16 小时前
olofk/serv
https://static.github-zh.com/github_avatars/olofk?size=40

SERV - The SErial RISC-V CPU

Verilog 1.64 k
3 个月前
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