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集合主题趋势排行榜
#

firrtl

Website
Wikipedia
chipsalliance/chisel
https://static.github-zh.com/github_avatars/chipsalliance?size=40
chipsalliance / chisel

Chisel: A Modern Hardware Design Language

chiselchisel3Scalafirrtlrtlchip-generatorVerilog
Scala 4.3 k
2 天前
https://static.github-zh.com/github_avatars/chipsalliance?size=40
chipsalliance / firrtl

Flexible Intermediate Representation for RTL

firrtlintermediaterepresentationhardwaretransformation编译器
Scala 744
10 个月前
https://static.github-zh.com/github_avatars/ucsc-vama?size=40
ucsc-vama / essent

high-performance RTL simulator

firrtlrtlchiselScala
Scala 159
1 年前
https://static.github-zh.com/github_avatars/freechipsproject?size=40
freechipsproject / diagrammer

Provides dot visualizations of chisel/firrtl circuits

chiselchisel3firrtl可视化
Scala 119
2 年前
https://static.github-zh.com/github_avatars/scutdig?size=40
scutdig / PyChip-py-hcl

A Hardware Construct Language

hardware-designsrtlVerilogPythonfirrtl
Python 43
3 年前
https://static.github-zh.com/github_avatars/thoughtworks?size=40
thoughtworks / hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

unumfloating-pointchiselchisel3ScalafirrtlVerilogrtlposit
C++ 39
2 个月前
https://static.github-zh.com/github_avatars/IBM?size=40
IBM / chiffre

A fault-injection framework using Chisel and FIRRTL

chiselfirrtlRISC-Vrocket-chipfault-injection
Scala 36
1 个月前
https://static.github-zh.com/github_avatars/grebe?size=40
grebe / ofdm

Chisel Things for OFDM

chiselchisel3Scalafirrtlrtlchip-generatorVerilog
Scala 32
5 年前
https://static.github-zh.com/github_avatars/hplp?size=40
hplp / aes_chisel

Implementation of the Advanced Encryption Standard in Chisel

aeschiselfirrtlVerilog
Scala 20
3 年前
https://static.github-zh.com/github_avatars/MaxXSoft?size=40
MaxXSoft / Bossa

BOOM's Simulation Accelerator.

boomRocketrocket-chipSimulationchipyardacceleratorchiselRISC-Vrtlsocverilatorfirrtl
Scala 14
4 年前
https://static.github-zh.com/github_avatars/CMU-SAFARI?size=40
CMU-SAFARI / Pythia-HDL

#计算机科学#Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al...

prefetcherVerilogScalachiselchisel3firrtlreinforcement-learning机器学习
Scala 13
4 年前
https://static.github-zh.com/github_avatars/MaxXSoft?size=40
MaxXSoft / Frenda

Split large FIRRTL into separated modules for incremental compilation.

firrtlchiselhardware编译器
Scala 10
4 年前
https://static.github-zh.com/github_avatars/chipsalliance?size=40
chipsalliance / tree-sitter-firrtl

FIRRTL grammar for tree-sitter

Tree-sitterParserfirrtl
C++ 9
1 年前
https://static.github-zh.com/github_avatars/IBM?size=40
IBM / firrtl-mode

Major mode for editing FIRRTL files in Emacs

firrtlEmacs
Emacs Lisp 8
2 年前
https://static.github-zh.com/github_avatars/jkopanski?size=40
jkopanski / firrtl

Haskell FIRRTL implementation

firrtlhardwareintermediate-representation
Haskell 3
6 年前
https://static.github-zh.com/github_avatars/seanpm2001?size=40
seanpm2001 / Learn-FIRRTL

📚️ A repository for showcasing my knowledge of the FIRRTL programming language, and continuing to learn the language.

firrtlgpl3GNU General Public License
FIRRTL 1
7 个月前
https://static.github-zh.com/github_avatars/seanpm2001?size=40
seanpm2001 / SNU_2D_ProgrammingTools_IDE_FIRRTL

#编辑器#⌨️ The FIRRTL programming language IDE submodule for SNU Programming Tools (2D Mode)

firrtlgpl3GNU General Public Licenseide编程web-development
FIRRTL 1
7 个月前
https://static.github-zh.com/github_avatars/jpsety?size=40
jpsety / obfuscation

A set of FIRRTL transforms for obfuscating circuits

chisel3firrtlobfuscation
Scala 1
6 年前
https://static.github-zh.com/github_avatars/nathsou?size=40
nathsou / yodl

Yet anOther hardware Description Language

chiselcircuitfirrtlfpgaVerilog
MoonBit 1
2 个月前
https://static.github-zh.com/github_avatars/lbnlcomputerarch?size=40
lbnlcomputerarch / mosaicfiresim

Chisel 6 and FIRRTL 2 wrapper for MoSAIC to integrate into FireSim

chiselfirrtlmosaic
Scala 1
1 个月前
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