rocket-chip · GitHub Topics

chipsalliance / rocket-chip

Rocket Chip Generator

Scala rocket-chip chip-generator chisel RISC-V rtl

Scala 3.5 k

2 个月前

riscv-boom / riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V boom chisel rtl rocket-chip Scala

Scala 1.95 k

3 个月前

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rocket-chip chip-generator chisel RISC-V rtl soc peripherals chipyard boom Rocket

Scala 1.92 k

4 天前

firesim / firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

fpga RISC-V Simulation datacenter hardware rocket-chip boom on-prem cloud

Scala 948

1 个月前

bu-icsg / dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

神经网络 rocket-chip hardware RISC-V rtl chisel

Scala 213

6 年前

eliaskousk / parallella-riscv

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards

RISC-V rocket-chip zynq Linux gsoc

SystemVerilog 102

7 年前

seldridge / rocket-rocc-examples

Tests for example Rocket Custom Coprocessors

RISC-V rocket-chip

C 75

5 年前

mit-ll / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

RISC-V Verilog fpga rocket-chip oshw soc chipyard

C 65

3 年前

li3tuo4 / rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

rocket-chip RISC-V

Tcl 62

2 年前

firesim / firechip

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

rocket-chip soc RISC-V

C 57

6 年前