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vlsi

Website
Wikipedia

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

asic magic yosys openroad skywater openram vlsi system-on-chip foundry rtl Verilog

Python 1.51 k

4 个月前

limbo018 / DREAMPlace

#计算机科学#Deep learning toolkit-enabled VLSI placement

深度学习 PyTorch vlsi gpu-acceleration

C++ 823

2 个月前

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

vlsi C++parallel-computing Verilog eda cad

Verilog 627

2 年前

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

vhdl poc-library Python Simulation synthesis verification vlsi fpga hardware-designs asic xilinx regression-testing

VHDL 580

5 年前

efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

asic eda gdsii lvs openroad pdk silicon Verilog vlsi flow

Python 294

4 个月前

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

Verilog vlsi vhdl GUI 逆向工程安全 Cybersecurity multi-platform chips C++cross-platform

C++ 260

7 个月前

arm-university / VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical impl...

microprocessor-implementation cadence-virtuoso synopsys-design arm computer-engineering electrical-engineering hardware-designs vlsi devices-circuits-materials

HTML 253

17 天前

nitram2342 / degate

Open source software for chip reverse engineering.

chip vlsi Verilog vhdl 可视化 GUI Library 图像处理 image-recognition 逆向工程

C++ 169

5 年前

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

Verilog 147

1 年前

phoeniX-Digital-Design / phoeniX

RISC-V Embedded Processor for Approximate Computing

computer-architecture fpga vlsi microprocessor RISC-V cpu embedded-systems

Verilog 126

17 天前

eelab-dev / EEcircuit

A browser-based SPICE circuit simulator

electronics circuit Simulation spice WebAssembly emscripten vlsi

TypeScript 125

8 天前

cuhk-eda / Xplace

Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization

eda placement gpu gpu-acceleration vlsi

C++ 125

21 天前

purdue-onchip / gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

gdsii Parsing eda vlsi

C++ 119

2 年前

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Python 114

2 年前

asyncvlsi / act

ACT hardware description language and core tools.

eda cad Verilog design-automation vlsi prs dataflow dataflow-programming language

C++ 110

21 天前

viktor-prutyanov / drec-fpga-intro

Материалы для курсов по проектированию цифровых вычислительных систем

Verilog fpga RISC-V 教学 asic vlsi

Verilog 96

2 个月前

NTU-LaDS-II / FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

eda C++Verilog vlsi 命令行界面 lex yacc

Verilog 90

2 年前

hsluoyz / Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

Verilog 81

1 年前

luckyrantanplan / nthu-route

VLSI EDA Global Router

vlsi router eda

C++ 73

7 年前

ahmed-agiza / EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

webgl Serverless hardware viewer eda 服务端渲染 cgo pixijs hardware-design vlsi lef def opendb-database layout

JavaScript 72

2 年前

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