vhdl · GitHub Topics

Digital logic design tool and simulator

logisim-evolution 教学 circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl Verilog

Java 5.84 k

6 天前

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl Verilog fpga

Assembly 2.8 k

7 天前

ghdl / ghdl

VHDL 2008/93/87 simulator

vhdl simulator 编译器 gcc LLVM hardware Hacktoberfest

VHDL 2.57 k

3 天前

cocotb / cocotb

cocotb: Python-based chip (RTL) verification

Python vhdl Verilog verification Testing

Python 2 k

2 天前

SpinalHDL / SpinalHDL

Scala based HDL

Scala rtl vhdl Verilog fpga

Scala 1.8 k

2 天前

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V vhdl fpga soc Microcontroller processor cpu system-on-chip embedded rtos smp multi-core Verilog

VHDL 1.79 k

2 天前

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

Haskell fpga vhdl Verilog systemverilog asic

Haskell 1.5 k

9 小时前

olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

Python eda Package manager fpga Verilog vhdl

Python 1.3 k

14 天前

drom / awesome-hdl

#Awesome#Hardware Description Languages

Awesome Lists Verilog vhdl Hacktoberfest

1.04 k

4 个月前

siliconcompiler / siliconcompiler

Modular hardware build system

asic eda fpga hls make rtl synthesis Verilog vhdl

Python 1.02 k

3 天前

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

vhdl verification systemverilog-hdl Unit testing fpga asic

VHDL 778

1 个月前

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

fpga ofdm wi-fi zynq Linux mac80211 csma dma Verilog hls xilinx analog-devices ad9361 sdr software-defined-radio ieee80211 hardware vhdl rtl

Verilog 763

1 个月前

nickg / nvc

VHDL compiler and simulator

vhdl simulator 编译器 fpga

C 704

4 天前

olofk / edalize

An abstraction library for interfacing EDA tools

eda fpga xilinx yosys synthesis Simulation Verilog vhdl systemverilog verilator

Python 695

4 天前

antonblanchard / microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

vhdl processor openpower ppc64le

Verilog 686

2 个月前

sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

RISC-V soc vhdl simulator systemc Qt cpu debugger

Verilog 667

16 天前

JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

fpga vhdl pipelines C Python hardware high-level-synthesis hls fpga-programming open-source-hardware

VHDL 656

7 天前

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Verilog vhdl systemverilog fpga

VHDL 621

2 个月前

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

vhdl poc-library Python Simulation synthesis verification vlsi fpga hardware-designs asic xilinx regression-testing

VHDL 580

5 年前

ben-marshall / awesome-open-hardware-verification

#Awesome#A List of Free and Open Source Hardware Verification Tools and Frameworks

hardware verification vhdl Verilog formal-verification Python Awesome Lists Test coverage

529

2 年前