risc

A graphical processor simulator and assembly editor for the RISC-V ISA

The RISC-V Virtual Machine

VeeR EH1 core

RISC-V simulator for x86-64

A fast, modern package manager for Static Binaries, Portable Formats (AppImage|AppBundle|FlatImage|Runimage) & More [maintainer=@QaidVoid]

RISC-V Assembler and Runtime Simulator

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

RISC-V instruction set simulator built for education

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

"Hacker's Delight" in Go

RISC-V Instruction Set Simulator (Built for education).

MRSIC32 ISA documentation and development

MikroLeo project files (schematic, PCB, assembler, emulator/debugger, circuit simulation file, documentation, example of programs etc). MikroLeo is a 4-bit microcomputer developed mainly for education...

OpenID Shared Signals Working Group Repository

#区块链#AluVM: RISC functional machine base implementation

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Project Oberon RISC emulator in Go

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.