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集合主题趋势排行榜
#

digital-logic

Website
Wikipedia
logisim-evolution/logisim-evolution
https://static.github-zh.com/github_avatars/logisim-evolution?size=40
logisim-evolution / logisim-evolution

Digital logic design tool and simulator

logisim-evolution教学circuitcircuitsdigital-circuitdigital-circuitssimulatorlogicdigital-logicdigital-logic-designfpgatiming-diagramlogisimvhdlVerilog
Java 6.18 k
20 小时前
https://static.github-zh.com/github_avatars/tilk?size=40
tilk / digitaljs

Teaching-focused digital circuit simulator

simulatorlogic-gatesdigital-logic
JavaScript 722
1 年前
https://static.github-zh.com/github_avatars/AnuragAnalog?size=40
AnuragAnalog / GateResources

#算法刷题#Here are my GATE CSE 2021 Resources

aptitudedigital-logic编程数据结构算法compiler-design操作系统dbmscn2021Hackathon-Kit
152
5 年前
https://static.github-zh.com/github_avatars/TimRudy?size=40
TimRudy / ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

edafpgaopen-hardwaredigital-logic
Verilog 146
10 个月前
https://static.github-zh.com/github_avatars/matijakevic?size=40
matijakevic / mcircuit

A digital logic simulator inspired by Logisim.

logisimSimulationsimulatorcircuitdigital-logicPythonQtLLVMpysidepyside6networkx
Python 50
4 年前
https://static.github-zh.com/github_avatars/Aparnaraha?size=40
Aparnaraha / Gate2024

#算法刷题#here the notes provided by the seniors who already cracked IITs as well as how much I'll cover for my exams I'll provide my notes as well. If you want you can access the course by these links also

算法aptitudecompiler-designNetwork数据结构database-managementdbmsdigital-logic操作系统编程toc
43
8 个月前
https://static.github-zh.com/github_avatars/TimRudy?size=40
TimRudy / uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

digital-logicedafpgaopen-hardwarehardware-designsserialport
Verilog 35
2 年前
https://static.github-zh.com/github_avatars/LevKruglyak?size=40
LevKruglyak / CircuitSimulator

Simple Java application for simulating digital circuits

computer-engineeringdigital-logicJava
Java 32
3 年前
https://static.github-zh.com/github_avatars/sabertazimi?size=40
sabertazimi / hust-lab

#算法刷题#Labs for Computer Science: C, Assembly, Data Structure, CSAPP, HSI, MATLAB, Digital Logic, Verilog, Compilers, Operating Systems

hustlab计算机科学算法AssemblyC编译器data-structruesdigital-logicVerilog函数式编程MATLAB操作系统
C 31
9 个月前
https://static.github-zh.com/github_avatars/fcayci?size=40
fcayci / vhdl-digital-design

VHDL code examples for a digital design course

vhdlfpgadigital-logic
VHDL 21
6 年前
https://static.github-zh.com/github_avatars/Martian-Technologies?size=40
Martian-Technologies / Connection-Machine

Connection Machine is an open-source desktop application for designing and simulating digital circuits at scale.

digital-circuit-designdigital-logic
C++ 20
5 天前
https://static.github-zh.com/github_avatars/Es1chUbJyan9?size=40
Es1chUbJyan9 / 32bit_Quine-McCluskey_and_Petrick_Method_in_C

32bit Simplifier of Boolean functions

Cdigital-logiclogic-programmingsimplification
C 19
7 年前
https://static.github-zh.com/github_avatars/Multimedia-Processing?size=40
Multimedia-Processing / Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。

vhdllearnfpgaVerilogsystemverilogxilinxxilinx-fpgadigital-logic-designdigital-logicdigital
Verilog 18
2 年前
https://static.github-zh.com/github_avatars/chaseruskin?size=40
chaseruskin / legoHDL

An experimental package manager and development tool for Hardware Description Languages (HDL).

Package managerVeriloghardware-designfpgavhdldigital-logic
Python 15
3 年前
https://static.github-zh.com/github_avatars/2catycm?size=40
2catycm / SUSTech-CS202_214-Computer_Organization-Project

This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology, which is to manufacture a CPU. 这是南方科技大学CS202...

cpudigital-logicmips
Verilog 15
3 年前
https://static.github-zh.com/github_avatars/dramforever?size=40
dramforever / finlog

Compiling finite generators to digital logic. WIP

Verilogdigital-logic编译器Haskell
Haskell 14
5 年前
https://static.github-zh.com/github_avatars/anuejn?size=40
anuejn / XC9500

WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

yosys逆向工程digital-logic
Python 10
4 年前
https://static.github-zh.com/github_avatars/xprova?size=40
xprova / xprova

Formal verification engine for Verilog with built-in support for simulating flip-flop metastability

formal-verificationdigital-logicVerilogmodel-checking
Java 9
8 年前
https://static.github-zh.com/github_avatars/djcopley?size=40
djcopley / QuineMcCluskey

A powerful tool for minimizing Boolean functions

digital-logicminimizationPython
Python 9
1 年前
https://static.github-zh.com/github_avatars/WilliamYi96?size=40
WilliamYi96 / SimpleComputer

The design and implementation of simple computer by quartus.

computerdigital-logicvhdl
VHDL 9
8 年前
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