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集合主题趋势排行榜
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xilinx-fpga

Website
Wikipedia
open-sdr/openwifi
https://static.github-zh.com/github_avatars/open-sdr?size=40
open-sdr / openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

fpgaofdm802-11zynqLinuxxilinxanalog-devicesmac80211csmadmaVeriloghlsopenwifiad9361sdrsoftware-defined-radioieee80211wifixilinx-fpgahardware
C 4.2 k
4 天前
https://static.github-zh.com/github_avatars/f4pga?size=40
f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.

fpgaxilinxxilinx-fpgaartixbitstream工具toolchainfuzzer
Python 804
11 天前
https://static.github-zh.com/github_avatars/f4pga?size=40
f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

fpgaice40sphinx文档Verilogxilinx-fpgaartixverilog-simulatorvprprimitivestoolchainsynthesisPython
Jupyter Notebook 289
6 天前
https://static.github-zh.com/github_avatars/ingonyama-zk?size=40
ingonyama-zk / blaze

blaze is a Rust library for ZK acceleration on Xilinx FPGAs.

Amazon Web Servicesfpgahardwarezero-knowledgexilinx-fpga
Rust 145
8 个月前
https://static.github-zh.com/github_avatars/ultraembedded?size=40
ultraembedded / openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

fpgalogic-analyzerxilinx-fpgaVerilog
Verilog 143
4 年前
https://static.github-zh.com/github_avatars/triSYCL?size=40
triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

xilinx-fpgaoneapi-dpcclangLLVMC++sycl
C++ 119
7 个月前
https://static.github-zh.com/github_avatars/derekmulcahy?size=40
derekmulcahy / xvcpi

Xilinx Virtual Cable Server for Raspberry Pi

zynqxilinx-fpga
C 114
3 年前
https://static.github-zh.com/github_avatars/ultraembedded?size=40
ultraembedded / core_ft60x_axi

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

Verilogfpgaxilinx-fpgausb3
C++ 94
5 年前
https://static.github-zh.com/github_avatars/chipsalliance?size=40
chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

yosysedafpgaxilinxxilinx-fpgatoolchain
Verilog 83
1 年前
https://static.github-zh.com/github_avatars/ultraembedded?size=40
ultraembedded / core_dvi_framebuffer

Minimal DVI / HDMI Framebuffer

hdmiVerilogfpgaxilinx-fpgaVideo
Verilog 81
5 年前
https://static.github-zh.com/github_avatars/f4pga?size=40
f4pga / prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

fpgaxilinxxilinx-fpgabitstreamfuzzer
SystemVerilog 78
3 年前
https://static.github-zh.com/github_avatars/f4pga?size=40
f4pga / prjxray-db

Project X-Ray Database: XC7 Series

fpgaxilinxxilinx-fpgaartixbitset工具toolchain数据库
Shell 69
4 年前
https://static.github-zh.com/github_avatars/diogofferreira?size=40
diogofferreira / fpga-miner

💰 A simplified version of an FPGA bitcoin miner 💰

fpgaxilinx-fpga
VHDL 52
6 年前
https://static.github-zh.com/github_avatars/pontazaricardo?size=40
pontazaricardo / Verilog_Calculator_Matrix_Multiplication

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

Verilogvhdlcalculatormatrix-multiplicationxilinxxilinx-fpgalow-level-programminghardware-designs
Verilog 49
8 年前
https://static.github-zh.com/github_avatars/fredrequin?size=40
fredrequin / verilator_xilinx

Re-coded Xilinx primitives for Verilator use

fpgaverilatorVerilogxilinx-fpga
Verilog 48
1 年前
https://static.github-zh.com/github_avatars/ingonyama-zk?size=40
ingonyama-zk / open-binius

building blocks for accelerating ZK proofs over binary fields

Cryptographyfpgahardwarexilinx-fpgazero-knowledge
Verilog 45
10 个月前
https://static.github-zh.com/github_avatars/stevenbell?size=40
stevenbell / csirx

Open-source CSI-2 receiver for Xilinx UltraScale parts

xilinx-fpga
Verilog 37
6 年前
https://static.github-zh.com/github_avatars/sailordiary?size=40
sailordiary / computer-systems-ucas

中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session

Verilogcpuxilinx-fpgacomputer-systems
Verilog 32
8 年前
https://static.github-zh.com/github_avatars/olivier-le-sage?size=40
olivier-le-sage / camera-filters

Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.

fpgaVeriloghdmixilinx-fpga
VHDL 30
5 年前
https://static.github-zh.com/github_avatars/KarenOk?size=40
KarenOk / SAP-1-Computer

Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.

vhdlfpgaxilinx-fpga
VHDL 29
2 年前
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