GitHub 中文社区
回车: Github搜索    Shift+回车: Google搜索
论坛
排行榜
趋势
登录

©2025 GitHub中文社区论坛GitHub官网网站地图GitHub官方翻译

  • X iconGitHub on X
  • Facebook iconGitHub on Facebook
  • Linkedin iconGitHub on LinkedIn
  • YouTube iconGitHub on YouTube
  • Twitch iconGitHub on Twitch
  • TikTok iconGitHub on TikTok
  • GitHub markGitHub’s organization on GitHub
集合主题趋势排行榜
#

digital-logic-design

Website
Wikipedia
logisim-evolution/logisim-evolution
https://static.github-zh.com/github_avatars/logisim-evolution?size=40
logisim-evolution / logisim-evolution

Digital logic design tool and simulator

logisim-evolution教学circuitcircuitsdigital-circuitdigital-circuitssimulatorlogicdigital-logicdigital-logic-designfpgatiming-diagramlogisimvhdlVerilog
Java 5.99 k
2 天前
https://static.github-zh.com/github_avatars/yupferris?size=40
yupferris / kaze

An HDL embedded in Rust.

Verilogdigital-logic-designRust
Rust 199
2 年前
https://static.github-zh.com/github_avatars/Akashtailor-exe?size=40
Akashtailor-exe / 30-days-of-verilog

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

30-days-of-code30daysofcodedigital-logic-designVerilogvlsirtl-design
43
2 年前
https://static.github-zh.com/github_avatars/MuxammilSidd?size=40
MuxammilSidd / FAST-KHI-Semester-2

FAST NUCES Karachi - BSCS Second Semester Repository | Access notes, assignments, past papers, & more. For queries or suggestions, contact k232001@nu.edu.pk.

digital-logic-designObject-oriented programming (OOP)semester-2
C++ 33
22 天前
https://static.github-zh.com/github_avatars/raycar5?size=40
raycar5 / logicsim

Composable digital logic simulation in Rust!

digital-logic-designRustcrates
Rust 32
5 年前
https://static.github-zh.com/github_avatars/madhurimarawat?size=40
madhurimarawat / Semester-Notes

This repository includes academic notes, study materials, and resources from B.Tech (Hons) in CSE, specializing in Artificial Intelligence and Data Science. It features question papers, proprietary st...

digital-logic-designentrepreneurshipcomputer-networkdatabase-management操作系统probability-statistics人工智能数据可视化Object-oriented programming (OOP)study-materials
HTML 28
1 个月前
https://static.github-zh.com/github_avatars/shrine-maiden-heavy-industries?size=40
shrine-maiden-heavy-industries / torii-hdl

A Python-based HDL and framework for silicon-based witchcraft

digital-logic-designfpgaVerilogyosys
Python 22
5 天前
https://static.github-zh.com/github_avatars/Multimedia-Processing?size=40
Multimedia-Processing / Digital-Logic-Design

透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。

vhdllearnfpgaVerilogsystemverilogxilinxxilinx-fpgadigital-logic-designdigital-logicdigital
Verilog 18
2 年前
https://static.github-zh.com/github_avatars/AryCra07?size=40
AryCra07 / TougHardware

BUPT 数字逻辑与数字系统课程设计项目

digital-logic-design
VHDL 12
2 年前
https://static.github-zh.com/github_avatars/Amey-Thakur?size=40
Amey-Thakur / DIGITAL-LOGIC-DESIGN-AND-ANALYSIS-AND-DIGITAL-SYSTEM-LAB

CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>

计算机科学engineeringcomputer-engineeringdigital-logic-designtextbooks
10
1 年前
https://static.github-zh.com/github_avatars/SM2A?size=40
SM2A / University_Projects

🎓💻All of my projects at University of Tehran

advanced-programmingdigital-logic-designcomputer-architecture人工智能compiler-design操作系统cadcomputer-graphicsNetwork
8
1 年前
https://static.github-zh.com/github_avatars/harismuneer?size=40
harismuneer / Car-Parking-Controller

🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"

digital-logic-designmuxopen-source-projectsignals
7
6 个月前
https://static.github-zh.com/github_avatars/rohankalbag?size=40
rohankalbag / vlsi-design

VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay

digital-logic-designvhdl
VHDL 7
2 年前
https://static.github-zh.com/github_avatars/skamal16?size=40
skamal16 / Mobile-Trainer-Board

My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.

digital-logic-designObject-oriented programming (OOP)JavaSimulationsimulator
Java 6
7 年前
https://static.github-zh.com/github_avatars/ShashankVM?size=40
ShashankVM / generic_systemverilog_designs_library

A library of useful, fully parameterized RTL designs implemented in SystemVerilog.

digital-logic-designsystemverilog
SystemVerilog 6
3 年前
https://static.github-zh.com/github_avatars/hasnainroopawalla?size=40
hasnainroopawalla / circuit-sim

Digital logic gate simulator using React, TypeScript and p5.js

digital-logic-designp5jsTypeScriptWebpackJavaScriptReactlogiclogic-gatessimulator
TypeScript 6
6 个月前
https://static.github-zh.com/github_avatars/ChaminduS?size=40
ChaminduS / Building-a-RISC-V-CPU-Core

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

RISC-Vdigital-logic-design
6
4 年前
https://static.github-zh.com/github_avatars/PashaBarahimi?size=40
PashaBarahimi / Digital-Logic-Design-Lab-Experiments

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

fpgadigital-logic-design
Verilog 5
3 年前
https://static.github-zh.com/github_avatars/Bh4r4t?size=40
Bh4r4t / 32-bit-Divider

32-bit Divider circuit implemented using Verilog

Verilogdigital-logic-design
Verilog 5
6 年前
https://static.github-zh.com/github_avatars/MohammadNiknam17?size=40
MohammadNiknam17 / UART_Receiver_Transmitter_Controller_VHDL-FPGA

VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.

uartfpgavhdltransmitterrammemorydigital-logic-design
VHDL 5
4 年前
loading...