Digital logic design tool and simulator
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
FAST NUCES Karachi - BSCS Second Semester Repository | Access notes, assignments, past papers, & more. For queries or suggestions, contact k232001@nu.edu.pk.
This repository includes academic notes, study materials, and resources from B.Tech (Hons) in CSE, specializing in Artificial Intelligence and Data Science. It features question papers, proprietary st...
A Python-based HDL and framework for silicon-based witchcraft
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
🎓💻All of my projects at University of Tehran
🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.
A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
Digital logic gate simulator using React, TypeScript and p5.js
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.