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chips

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#安卓#Implementation of Material Design Chips component for Android

Java 2.62 k
2 年前
https://static.github-zh.com/github_avatars/tylersuehr7?size=40

#安卓#A customizable Android ViewGroup for displaying Chips (specified in the Material Design Guide).

Java 585
6 年前
https://static.github-zh.com/github_avatars/DegateCommunity?size=40

A modern and open-source cross-platform software for chips reverse engineering.

C++ 266
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Nintendo Entertainment System (NES) / Famicom / Famiclones chip reversing

Verilog 186
3 个月前
https://static.github-zh.com/github_avatars/davigmacode?size=40

Lite version of smart_select package, zero dependencies, an easy way to provide a single or multiple choice chips.

Dart 114
2 年前
https://static.github-zh.com/github_avatars/viclafouch?size=40

📌 A chips input designed for MUI (Material ui) V6

TypeScript 90
5 个月前
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Computer built from the ground up on top of own CPU, while compiler and assembler for it implemented in Rust language

Assembly 77
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JavaScript 62
2 年前
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Versatile tool to untangle wires. Made by chip researchers - for chip researchers. This means that the utility is wildly custom and incomprehensible.

C# 56
1 个月前
https://static.github-zh.com/github_avatars/usnistgov?size=40

Evaluation of universal machine learning force-fields https://doi.org/10.1021/acsmaterialslett.5c00093

Python 45
2 个月前
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Java 45
5 年前
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BMBurner is a Arduino based EPROM Programmer SST 27SF512, 27C256, 27C512, 27SF256, 29C256, W27E512, W27C512, DS1230, 62C256, etc..

39
5 年前
https://static.github-zh.com/github_avatars/emu-russia?size=40

Reverse engineering of the SONY PlayStation CPU (WIP)

C++ 31
4 个月前
https://static.github-zh.com/github_avatars/davigmacode?size=40

The successor to smart_select and chips_choice with cleaner, more flexible, and composable API for creating inline or prompted choice widgets with single or multiple selection.

Dart 27
1 年前
https://static.github-zh.com/github_avatars/andkorzh?size=40

A highly clock-accurate FPGA clone of the NES 2C02(7) PPU, created on the basis of reverse engineering.

Verilog 27
14 天前
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A highly clock-accurate FPGA clone of the NES 2A03(7) APU (pAPU), created on the basis of reverse engineering.

Verilog 23
2 个月前
https://static.github-zh.com/github_avatars/xdev-software?size=40

A ComboBox with Chips/Chip Components for Vaadin Flow

Java 22
1 年前
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