#

artix-7

https://static.github-zh.com/github_avatars/ultraembedded?size=40

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

C 281
5 年前
https://static.github-zh.com/github_avatars/ultraembedded?size=40

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Verilog 57
5 年前
https://static.github-zh.com/github_avatars/Mario-Hero?size=40

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

Verilog 30
5 年前
https://static.github-zh.com/github_avatars/j3soon?size=40
VHDL 24
2 年前
https://static.github-zh.com/github_avatars/briansune?size=40
22
7 个月前
https://static.github-zh.com/github_avatars/liolok?size=40

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

Verilog 14
6 年前
https://static.github-zh.com/github_avatars/chipsalliance?size=40

Library to convert a FASM file into BELs importable into Vivado.

Verilog 13
2 年前
https://static.github-zh.com/github_avatars/7enTropy7?size=40

My experiments with Nexys4 DDR Artix-7 FPGA Board

Verilog 8
5 年前
https://static.github-zh.com/github_avatars/raleighlittles?size=40

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

Verilog 8
4 年前
https://static.github-zh.com/github_avatars/Chrisdeleon91?size=40

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

VHDL 7
3 年前
https://static.github-zh.com/github_avatars/whutddk?size=40

基于蜂鸟E203的魔改

Verilog 7
6 年前
https://static.github-zh.com/github_avatars/SnrNotHere16?size=40

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

VHDL 6
3 年前
https://static.github-zh.com/github_avatars/Prajjv?size=40

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

Tcl 5
3 年前
https://static.github-zh.com/github_avatars/hglee?size=40
SystemVerilog 5
2 年前
https://static.github-zh.com/github_avatars/Yazmau?size=40

A tetris-game on screen using verilog.

Verilog 5
6 年前
https://static.github-zh.com/github_avatars/cajt?size=40

GRLIB GPL support for Digilent CMOD A7 35T board

VHDL 5
6 年前
https://static.github-zh.com/github_avatars/whutddk?size=40

A PCB platform based on the architecture of Arm + FPGA

HTML 5
6 年前
loading...
Website
Wikipedia