artix-7 · GitHub Topics

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

RISC-V rv32i rv32im cpu fpga Verilog verilator asic branch-prediction Linux xilinx artix-7

Verilog 1.04 k

4 年前

ultraembedded / FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

fpga fpga-media-player jpeg-decoder sd-card RISC-V mjpeg rtos artix-7 hdmi vga

C 279

5 年前

ultraembedded / usb2sniffer

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

usb fpga rtl Verilog artix-7 wireshark

Verilog 55

5 年前

vankxr / icyradio

Over-engineered SDR development board

fpga sdr software-defined-radio ice40 ad9361 artix-7 cm4 hardware Verilog mmwave usb-pd

VHDL 41

7 个月前

Mario-Hero / Async-Karin

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

fpga asynchronous async Verilog artix-7

Verilog 30

5 年前

j3soon / Handwritten-Digit-Recognition-Painter

#计算机科学#A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

Verilog artix-7 embedded embedded-systems fpga 人工智能深度学习机器学习神经网络

VHDL 24

2 年前

briansune / FPGA-Camera-MIPI-DVP-Verilog

FPGA Camera Parallel & MIPI Verilog

fpga Verilog xilinx artix-7 ov2640

4 个月前

liolok / HDU_CO_Guide

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

artix-7 Verilog

Verilog 14

6 年前

chipsalliance / f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

fasm tcl Verilog bitstream artix-7

Verilog 13

2 年前

briansune / Artix-7-PCIE-Riffa

artix-7 fpga Verilog pcie xilinx

Verilog 9

3 年前

7enTropy7 / Artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

fpga-programming Verilog artix-7

Verilog 8

5 年前

raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

fpga artix-7 Verilog

Verilog 8

3 年前

Chrisdeleon91 / Xilinx-Artix-7-PCIe-Project

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

vhdl artix-7 xilinx

VHDL 7

2 年前

whutddk / verilogRisc

基于蜂鸟E203的魔改

RISC-V artix-7

Verilog 7

6 年前

SnrNotHere16 / FPGADivisionFloatingPoint

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

fpga xilinx floating-point artix-7 microblaze zynq SDK C Verilog division

VHDL 6

3 年前

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..

artix-7 microprocessor RISC-V Verilog vivado-hls

Tcl 5

3 年前