rtl-design · GitHub Topics

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

30-days-of-code 30daysofcode digital-logic-design Verilog vlsi rtl-design

2 年前

snbk001 / 100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge d...

makefile systemverilog rtl-design Verilog synthesis systemverilog-hdl

SystemVerilog 34

3 年前

synogate / gatery

Gatery, a library for circuit design.

rtl rtl-design vlsi asic fpga C++Library

C++ 19

6 个月前

AUCOHL / RTL-Repo

#大语言模型#RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

大语言模型 rtl-design Verilog

Python 14

1 年前

maazm007 / 100Daysof_RTL

The Repository contains the code of various Digital Circuits

Verilog rtl-design

Verilog 10

2 年前

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM...

questasim rtl rtl-design Verilog Finite-state machine synthesis systemverilog

Verilog 8

10 个月前

esynr3z / pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

pip Python rtl-design systemverilog verification Verilog vhdl vip

Python 7

1 年前

Luca-Dalmasso / DLX

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

vhdl computer-architecture embedded-systems hardware-designs rtl-design

Verilog 6

2 年前

cp024s / 100-days-of-RTL

probable journey of RTL coding ft. Chandra Prakash

fpga-programming systemverilog Verilog fpga rtl-design

Verilog 6

1 年前

MohamedHussein27 / AMPA_APB4_Protocol

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simul...

communication-protocol rtl-design

Verilog 6

9 个月前

synogate / gatery_template

Template project for using gatery

rtl rtl-design vlsi asic fpga C++

C++ 4

8 个月前

Ammar-Bin-Amir / AXI4

RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle

rtl-design Verilog

Verilog 4

1 年前

MohamedHussein27 / RISC-V-Single-Cycle-Implementation

This repository features a self-designed and enhanced single-cycle RISC-V processor, developed based on the Digital Design and Computer Architecture RISC-V Edition book.

computer-architecture rtl-design

Verilog 4

5 个月前

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and Syst...

图像处理 object-oriented Object-oriented programming (OOP)systemc rtl-design

C++ 3

3 年前