30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

30-days-of-code 30daysofcode digital-logic-design Verilog vlsi rtl-design

2 年前

snbk001 / 100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge d...

makefile systemverilog rtl-design Verilog synthesis systemverilog-hdl

SystemVerilog 35

3 年前

synogate / gatery

Gatery, a library for circuit design.

rtl rtl-design vlsi asic fpga C++Library

C++ 21

9 个月前

dannydyl / SONY-Cell-SPU-Processor

This repository contains the complete Verilog implementation and supporting tools for a cycle-accurate, dual-issue pipelined multimedia processor inspired by the Synergistic Processing Unit (SPU) of t...

computer-architecture cpu-architecture processor rtl-design simd Verilog vlsi

Verilog 18

4 个月前

AUCOHL / RTL-Repo

#大语言模型#RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24

大语言模型 rtl-design Verilog

Python 17

1 年前

maazm007 / 100Daysof_RTL

The Repository contains the code of various Digital Circuits

Verilog rtl-design

Verilog 11

2 年前

MohamedHussein27 / AMPA_APB4_Protocol

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simul...

communication-protocol rtl-design

Verilog 9

1 年前

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM...

questasim rtl rtl-design Verilog Finite-state machine synthesis systemverilog

Verilog 8

1 年前

esynr3z / pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

pip Python rtl-design systemverilog verification Verilog vhdl vip

Python 8

2 年前

cp024s / 100-days-of-RTL

probable journey of RTL coding ft. Chandra Prakash

fpga-programming systemverilog Verilog fpga rtl-design

Verilog 7

2 年前

Luca-Dalmasso / DLX

RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor

vhdl computer-architecture embedded-systems hardware-designs rtl-design

Verilog 6

3 年前

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and Syst...

图像处理 object-oriented Object-oriented programming (OOP)systemc rtl-design

C++ 6

3 年前