synopsys · GitHub Topics

limerainne / Dockerize-EDA

[WIP] Dockerize Synopsys/Cadence EDA tools

Dockerfile eda synopsys cadence

Dockerfile 89

6 年前

foss-for-synopsys-dwc-arc-processors / embarc_osp

embARC Open Software Platform (OSP) - An embedded software distribution for IoT and other embedded applications for ARC

iot-platform iot-framework arc Internet of things synopsys

C 78

1 年前

bojackchen / digital-flow

This is a tutorial on standard digital design flow

timing-analysis synopsys synthesis

Tcl 78

4 年前

kaushalmodi / custom_uvm_report_server

Customized UVM Report Server

systemverilog cadence synopsys vcs

SystemVerilog 40

5 年前

mperov / fixSegfaultVCS

There is segmentation fault of VCS which should be fixed.

synopsys vcs

Python 35

2 年前

Juanx65 / RISC-V

Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.

RISC-V synopsys Visual Studio Code

Verilog 23

1 年前

iDoka / book-mastering-fpgasic

📖 Mastering FPGASIC Book

fpga asic vlsi book Verilog vhdl xilinx intel synopsys cadence hardware engineering diy

4 年前

minhoolee / Synopsys-Project-2017

#计算机科学#A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.

深度学习 Bioinformatics synopsys Keras

Jupyter Notebook 17

2 年前

erihsu / tf-parser

Technology file parser in Rust

nom Parser synopsys

Rust 13

4 年前

kkiningh / synthesis-example

Example of a full DC synthesis script for a simple design

vlsi Verilog synthesis synopsys

Tcl 12

6 年前

gabrielganzer / RTL-PowerOptimization

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

optimization tcl Script synopsys Project

Verilog 11

4 年前

lnishan / Curriculum-Vitae

🌟 Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown

curriculum-vitae taiwan Google synopsys 计算机科学教学 internship competitive-programming programming-contests skills

CSS 10

7 年前

rabieifk / Synthesis-and-TCL-Scripting

Exploring Synopsys(R) synthesis tools

synopsys cad mips

Verilog 8

5 年前

gabrielganzer / DLX-Microprocessor

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout us...

synthesis microprocessor optimization synopsys cadence

Verilog 8

4 年前