Risc-V Cores-集合 | GitHub 中文社区

Risc-V Cores

The market for processors and microcontrollers is increasingly heated, and with the launch of the ISA (Instruction Set Achitecture) RISC-V, an open specification, it opens up a new opportunity for those who want to act either by researching or collaborating with new processors and microcontrollers.

Those who master the synthesis of Hardware with FPGA, can also propose more concretely new approaches for microcontrollers taking advantage of codes already written for the new architecture.

In this collection I try to present some renowned cores, and open the opportunity for other colleagues to collaborate with their suggestions.

picorv32

Yosys Headquarters@YosysHQ

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog3.54 k

1 年前

rocket-chip

@chipsalliance

Rocket Chip Generator

Scala rocket-chip chip-generator chisel RISC-V

Scala3.47 k

1 个月前

VexRiscv

@SpinalHDL

A FPGA friendly 32 bit RISC-V CPU implementation

RISC-V soc cpu vhdl

Assembly2.81 k

15 天前

riscv-isa-sim

@riscv-software-src

Spike, a RISC-V ISA Simulator

C2.73 k

4 天前

e200_opensource存档

@SI-RISCV

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

RISC-V cpu core china

Verilog2.73 k

4 年前

cva6

@openhwgroup

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

systemverilog-hdl cpu asic fpga rv64gc

Assembly2.52 k

6 天前

darkriscv

@darklife

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V Verilog fpga core

Verilog2.35 k

1 天前

riscv-boom

@riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V boom chisel rtl rocket-chip

Scala1.92 k

2 个月前

neorv32

@stnolting

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC-V vhdl fpga soc

VHDL1.79 k

1 天前

serv

@olofk

SERV - The SErial RISC-V CPU

Verilog fpga asic RISC-V

Verilog1.6 k

19 天前

ibex

@lowRISC

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

hardware RISC-V

SystemVerilog1.55 k

25 天前

riscv

@ultraembedded

RISC-V CPU Core (RV32IM)

RISC-V cpu Verilog fpga verilator

Verilog1.48 k

4 年前

NutShell

@OSCPU

RISC-V SoC designed by students in UCAS

Scala1.46 k

6 个月前

tinyriscv

@liangkangnan

A very simple and easy to understand RISC-V core.

C1.26 k

2 年前

freedom存档

@sifive

Source files for SiFive's Freedom platforms

Scala1.12 k

4 年前

cv32e40p

@openhwgroup

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V

SystemVerilog1.08 k

1 个月前

rsd

@rsd-devel

RSD: RISC-V Out-of-Order Superscalar Processor

SystemVerilog1.06 k

4 个月前

biriscv

@ultraembedded

32-bit Superscalar RISC-V CPU

RISC-V rv32i rv32im cpu

Verilog1.04 k

4 年前

scr1

@syntacore

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

RISC-V rtl Verilog rv32i

SystemVerilog919

7 个月前

Cores-VeeR-EH1

@chipsalliance

VeeR EH1 core

processor risc RISC-V

SystemVerilog884

2 年前

riscv-qemu存档

@riscvarchive

QEMU with RISC-V (RV64G, RV32G) Emulation Support

C387

6 年前

RV12

@RoaLogic

RISC-V CPU Core

RISC-V 64bit cpu

SystemVerilog326

1 年前

minerva

@minerva-cpu

A 32-bit RISC-V soft processor

Python294

1 年前

warp-v

@stevehoover

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

TL-Verilog223

1 年前

rvx

@rafaelcalcada

RISC-V microcontroller IP core developed in Verilog

RISC-V rv32i core uart

Verilog174

2 个月前

RPU

@Domipheus

Basic RISC-V CPU implementation in VHDL.

fpga cpu vhdl RISC-V

VHDL166

5 年前

riscy-OOO

@csail-csg

RiscyOO: RISC-V Out-of-Order Processor

Bluespec155

5 年前

riskow

@racerxdl

Learning how to make a RISC-V

fpga learning-exercise opencore RISC-V

Verilog134

4 年前

mriscv

@onchipuis

A 32-bit Microcontroller featuring a RISC-V core

Verilog130

7 年前

dinocpu

@jlpteaching

A teaching-focused RISC-V CPU design used at UC Davis

Scala103

2 年前

chiselv

@carlosedp

A RISC-V Core (RV32I) written in Chisel HDL

RISC-V fpga core chisel

Scala102

3 个月前

lizard

@cornell-brg

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

Python87

6 年前

RISC-V_MYTH_Workshop

@stevehoover

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

TL-Verilog79

1 年前

ReonV

@lcbcFoo

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

VHDL78

3 年前

kronos

@SonalPinto

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

SystemVerilog75

2 年前

T13x

@klessydra

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compa...

VHDL38

2 年前