openroad · GitHub Topics

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opendb-database openroad lef Verilog timing-analysis def eda rtl gdsii C++tcl

Verilog 2.15 k

3 小时前

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

eda rtl tcl def gdsii Verilog openroad timing-analysis lef opendb-database

Verilog 487

1 天前

efabless / caravel

Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys openroad openram

Verilog 346

6 个月前

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic openram openroad yosys

Verilog 137

4 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

7 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda openroad pdk

Verilog 26

3 年前

meeeeet / RTL-to-GDS-Implementation-of-SerDes

openroad Verilog

Verilog 20

2 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0

9 track standard cells for GF180MCU provided by GlobalFoundries.

asic eda openroad pdk

Verilog 18

3 年前

google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram

SRAM macros created for the GF180MCU provided by GlobalFoundries.

asic eda ip openroad pdk

Verilog 17

2 年前

google / skywater-pdk-libs-sky130_fd_sc_hd

"High density" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 16

3 年前

google / globalfoundries-pdk-libs-gf180mcu_fd_io

IO and periphery cells for the GF180MCU provided by GlobalFoundries.

asic eda io openroad pdk

Verilog 14

3 年前

google / skywater-pdk-libs-sky130_fd_sc_hdll

"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 7

4 年前

google / skywater-pdk-libs-sky130_fd_sc_lp

"Low power" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 7

4 年前

google / skywater-pdk-libs-sky130_fd_sc_ls

"Low speed" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 5

4 年前

google / skywater-pdk-libs-sky130_fd_sc_hs

"High speed" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 5

4 年前

google / skywater-pdk-libs-sky130_fd_sc_ms

"Medium speed" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 5

4 年前

google / skywater-pdk-libs-sky130_fd_sc_hvl

"High voltage" digital standard cells for SKY130 provided by SkyWater.

asic eda openroad silicon

Verilog 4

4 年前

abdelrahmanhosny / FlowRunnerAESExample

Running OpenROAD cloud flow on AES design

openroad eda cloud 自动化

Verilog 2

6 年前

Pa1mantri / VSDMemSOC

VSDMemSOC Implementation flow:: RTL2GDSII

gdsii macros openroad RISC-V yosys

Verilog 1

2 年前