ghdl / ghdl-yosys-plugin

VHDL 2008/93/87 simulator

Yosys Open SYnthesis Suite

Helps to import KiCad component libraries imported from ultralibrarian and snapeda zipfiles.

Multi-platform nightly builds of open source digital design and verification tools

Documenting Lattice's 28nm FPGA parts

Universal utility for programming FPGA

A modern hardware definition language and toolchain based on Python

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

OpenSCAD 是一个用于创建实体三维CAD 对象的软件。它是普适的一个软件，支持Linux/UNIX、Windows 和 Mac OS X

Python library for communicating with Huawei SUN2000 inverters - mirror of https://gitlab.com/Emilv2/huawei-solar/

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Verilog I2C interface for FPGA implementation

I2C models for cocotb

Demo SoC for SiliconCompiler.

Magic VLSI Layout Tool

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Modular hardware build system

A collection of big designs to run post-synthesis simulations with yosys