ultraembedded / core_ddr3_controller

RISC-V CPU Core (RV32IM)

32-bit Superscalar RISC-V CPU

Various HDL (Verilog) IP Cores

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Code for the ICLR 2023 paper "GPTQ: Accurate Post-training Quantization of Generative Pretrained Transformers".

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

A simple DDR3 memory controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Code repo for the paper "LLM-QAT Data-Free Quantization Aware Training for Large Language Models"

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

#计算机科学#A machine learning software for extracting information from scholarly documents

Reverse Engineering: Decompiling Binary Code with Large Language Models

一个用于将整个网页保存为单个HTML文件的命令行工具

SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

#大语言模型#20+ high-performance LLMs with recipes to pretrain, finetune and deploy at scale.

Cortex M0 based SoC

Image Processing Toolbox in Verilog using Basys3 FPGA

Controller SDIo host compatible with wishbone I/F {verilog}

Step by step tutorial for building CortexM0 SoC

Point Cloud Library (PCL)

A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs