SystemRDL / PeakRDL-html

Generate UVM register model from compiled SystemRDL input

Import and export IP-XACT XML register models

Control and status register code generator toolchain

SystemRDL 2.0 language compiler front-end

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

A Hardware Construct Language

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

#计算机科学#Machine learning on FPGAs using HLS

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

#安卓#Joplin 是一个用来记录笔记和待办事项的应用软件，支持Windows，macOS，Linux，Android和iOS

RePlAce global placement tool

Conan - The open-source C and C++ package manager

#编程语言#Julia 是一款为满足高性能数值分析和计算科学的需要而设计的编程语言。

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.