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openrisc

https://static.github-zh.com/github_avatars/s-macke?size=40

Online OR1K Emulator running Linux

JavaScript 1.76 k
3 年前
https://static.github-zh.com/github_avatars/openrisc?size=40

mor1kx - an OpenRISC 1000 processor IP core

Verilog 553
25 天前
https://static.github-zh.com/github_avatars/optimsoc?size=40

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

C 85
5 年前
https://static.github-zh.com/github_avatars/kuopinghsu?size=40
Assembly 38
2 年前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

Multi-Processor System on Chip verified with UVM/OSVVM/FV

SystemVerilog 34
4 个月前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

System on Chip verified with UVM/OSVVM/FV

SystemVerilog 31
4 个月前
https://static.github-zh.com/github_avatars/ilyakurdyukov?size=40

OpenRISC 1000 processor module for IDA 7.x

Python 13
2 年前
https://static.github-zh.com/github_avatars/janweinstock?size=40

An OpenRISC 1000 Instruction Set Simulator

C++ 13
6 个月前
https://static.github-zh.com/github_avatars/bandvig?size=40

OpenRISC processor IP core based on Tomasulo algorithm

Verilog 11
4 年前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

Processing Unit verified with UVM/OSVVM/FV

SystemVerilog 5
4 个月前
https://static.github-zh.com/github_avatars/andrakis?size=40

Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.

C++ 4
6 年前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

SystemVerilog 2
4 个月前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

Processing Unit with OpenRISC-32 / OpenRISC-64

SystemVerilog 2
4 个月前
https://static.github-zh.com/github_avatars/snps-virtualprototyping?size=40

OpenCpuX wrapper for the or1kiss OpenRISC ISS

C++ 2
6 年前
https://static.github-zh.com/github_avatars/bandvig?size=40

FPU verification tool for OpenRISC based on softfloat library

C 1
6 年前
https://static.github-zh.com/github_avatars/PacoReinaCampo?size=40

System on Chip with OpenRISC-32 / OpenRISC-64

SystemVerilog 1
4 个月前
https://static.github-zh.com/github_avatars/lucasasselli?size=40

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software ...

Verilog 1
4 年前
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