pConst / basic_verilog

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Verilog Ethernet components for FPGA implementation

Icarus Verilog

Verilog PCI express components

training labs and examples

IC design and development should be faster，simpler and more reliable

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Verilog library for ASIC and FPGA designers

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Haskell to VHDL/Verilog/SystemVerilog compiler

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

一群反对“996”工作制的人，发起的一个项目

PicoRV32 - A Size-Optimized RISC-V CPU

香山（XiangShan）是一款开源的高性能 RISC-V 处理器