mohamedazizbelhouchet / RISC-V-PIPELINED-PROCESSOR-Implementation

An AI-powered, but model-agnostic name-entity recognition toolkit.

A verilog HDL based project to control a servomotor with voice commands from an android phone.

This project is a digital design project that implements a simple programmable stepper motor controller using the Verilog hardware description language (HDL) and the Basys 3 FPGA development board. Th...

The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 inst...

IEEE Carleton Intro to Vivado workshop: In this workshop, you will be designing a basic Verilog circuit for the Nexys-A7-100t. The design will make use of clock dividers, multiplexers, bit-shifting an...

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...

(Capstone Masters Project) Image Matching utilizing fast 1-D 256-point discrete cosine transform (DCT) running at 100MHz. The 256-point DCT has 16 layers with 128 operations each. Images are processed...

In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardware description language.

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog