复旦大学 数字逻辑与部件设计实验 2020秋
交通大學iclab 2023 fall
Verilog codes developed as a part of COA lab course
This repository contains the projects which I created using Verilog
RV32I 5-Stage Pipelined CPU
Verilog HDL implementation and verification of a controller unit of washing machine.
Freshman course DCD in NYCU; 2022
Digital circuits design (HDL) ⚡