Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
Kite: Architecture Simulator for RISC-V Instruction Set
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
Computer architecture related projects
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
2 bit saturated branch predictor with BHR (Branch History Register)
C++ Instruction Set Simulator for RISC-V RV32IMC & custom SIMD instructions with cache and branch predictor models, C/ASM workloads, and Python analysis tools
C++ Macro definitions for easy branch hinting.
Compares execution speed of processing sorted and unsorted arrays, with and without branching. Disassembly and results included.
Implemented an algorithm to simulate the use of dynamic branch prediction schemes
Trabalhos apresentados como requisito parcial à conclusão da disciplina "CI086 - Tópicos em Arquitetura de Computadores" da UFPR, feitos no ambiente do simulador de instruções Orcs. A referência mais ...